
# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator

hdi::project new -name ISE_Scanner_Project -dir "F:/Tesis/FPGA/patmp"
hdi::project setArch -name ISE_Scanner_Project -arch spartan3e
hdi::design setOptions -project ISE_Scanner_Project -top netlist_1_EMPTY
hdi::param set -name project.paUcfFile -svalue "Nexys2_500General.ucf"
hdi::floorplan new -name floorplan_1 -part xc3s500efg320-5 -project ISE_Scanner_Project
hdi::port import -project ISE_Scanner_Project -verilog {ISE_Scanner_Project_pa_ports.v work}
hdi::pconst import -project ISE_Scanner_Project -floorplan floorplan_1 -file "Nexys2_500General.ucf"
